Modern semiconductor device packages are formed from multiple stacked layers of materials that may include numerous electrically active components that are electrically coupled together by metal conductor interconnects. Although aluminum conductors with silicon dioxide disposed between such interconnects have been used in the past, current practices in fabricating high speed semiconductor devices and have moved toward using a combination of copper interconnects with suitable dielectric insulating materials or films such as low-k dielectrics to take advantage of the superior conductivity of copper compared to aluminum and reduced parasitic capacitance between the conductors. This has reduced resistive capacitance delay (“RC delay”) which limits increases in clock speed in integrated circuits and semiconductor devices.
Back end-of-line (“BEOL”) processes are used to create the intricate network of conductor interconnects in each layer and between the multiple layers wherein copper is laid into the dielectric material. An additive patterning processes, referred to as damascene and dual damascene, are some BEOL process used to form the patterned copper conductor interconnect circuit(s) which interconnect various active components (e.g., resistors, transistors, etc.) disposed in the single and multiple layers throughout the microchip. Some of these interconnect circuit structures include trenches which are formed and then filled with the copper conductor and vias which are essentially metal-plated or filled holes that electrically interconnect the conductors interspersed between the multiple layers in the semiconductor packages.
Line-to-line capacitance between nearby interconnect lines has become an increasingly limiting factor on microprocessor clock speeds as semiconductor fabrication processes have been scaled down, for example to current 90 nm (nanometer) and 65 nm processes, and new 45 nm process. Low-k (LK) dielectric materials, such as Black Diamond® available from Applied Materials, Incorporated® which has a dielectric constant (k) lower than 3, have been used for forming ILD (inter-layer dielectric) or IMD (inter-metal dielectric) layers to better electrically isolate interconnects and reduce line-to-line capacitance for 90 nm and below processes, thereby concomitantly reducing resistive capacitance delay (RC delay) which hinders processor speeds. Further reduction of RC delay has been attempted by the introduction of more porous extreme low-k (ELK) and ultra low-k (ULK) dielectric materials (k generally equal to or less than about 2.5) such as Black Diamond II® which are targeted for the newer 45 nm process. Although the porosity introduced into these latter ELK and ULK dielectric materials further improves interconnect isolation by lowering the dielectric constant k, it also decreases the mechanical modulus making these materials more brittle that prior low-k materials and susceptible to damage such as cracking. The LK dielectric materials in general also have lower adhesive properties resulting in weaker bonding to other adjoining layers of semiconductor materials than traditional oxide dielectrics making the low-k materials more prone to delamination.
The semiconductor fabrication process entails forming a plurality of integrated circuit (IC) chips or dies on a single semiconductor wafer. These dies are later separated through a process known as die cutting or singulation in which typically a mechanical or laser saw is used to make cuts through the wafer between individual chips. To facilitate the die separation process, relatively narrow sacrificial scribe bands or streets are provided on the wafer along which the cuts are made to separate the chips.
To facilitate wafer level testing before the die separation process, the conductive paths of multi-layer interconnect structures formed within the dies are typically terminated in conductive bond or test pads disposed at the surface of the die. These “process control monitor” (PCM) test pads allow various electrical tests to be performed to monitor the complex semiconductor fabrication process and check the reliability of the dies before singulation. A multitude of test pads are typically distributed throughout the top surface of the wafer.
One conventional design approach for semiconductor wafers is to locate the test pads within and along sacrificial scribe bands or streets that typically traverse the wafer between the IC dies, as shown for example in FIGS. 1 and 2. During the die singulation process in which the individual dies are separated from the wafer, saw cuts are made along the scribe bands and pass directly through the test pads severing the pads. This process, however, produces mechanical stresses when the test pads are severed sometimes resulting in physical defects that may propagate into the dies adjacent the scribe bands and pads. For example, cracks and peeling may originate at the severed test pad when cut by the saw which then propagates to the dies. The cracking and peeling problems are often most acute at the corners of dies located at the intersection of scribe bands or streets. The saw-cut induced stresses can variously be manifested as cracking, chipping, flaking, peeling, and/or delamination of the layered semiconductor materials at the edges of the dies. The foregoing defects can further propagate more deeply into the die well beyond the die edges. Such defects adversely effects die reliability and increases die failure and rejection rates. Moreover, as noted above, low-K materials such as ELK and ULK dielectrics when used are especially susceptible to cracking, delamination, or the other foregoing defects due to non-adhesive and brittle nature of these insulting materials.
One conventional approach to mitigate the die cracking and peeling problem has been to incorporate separate protective structures or barriers into the wafer as shown in FIGS. 1 and 2, as further described generally in U.S. Patent Application Publication No. 2006/0125059 which in incorporated herein by reference in its entirety. These protective barriers may be made of metal and extend through multiple interconnect layers of the wafer. The barriers are generally linear in shape (top view) and may be continuous or interrupted in configuration as shown. As shown in FIGS. 1 and 2 herein, the barriers may extend along several PCM test pads and are located between the test pads and the dies within the scribe bands or streets to intercept cracks or peeling originating from the test pads when saw cut during the die singulation process. These protective barriers, however, occupy valuable space on the wafer within the scribe bands or streets which is contrary to the goal of providing minimum spacing between nearby dies to maximize the total number of dies that can be built on the wafer. For example, the N65 wafer fabrication process requirements dictate that the scribe bands or streets typically be about 60-80 microns wide providing margins between the edges of the PCM test pads and dies ranging from about 10-20 microns in width, depending on the width of the test pads. This spacing does not account for providing the additional surface space necessary to accommodate separate protective barrier structures within the scribe bands or streets, which consumes additional valuable surface space and require that the scribe bands be even wider.
An improved semiconductor structure is desired that reduces the potential for die defect formation resulting from the singulation process and that consumes less wafer surface space than conventional protective structures or barrier.